1. Field of the Invention
The present invention is related to a reference voltage generation circuit for generating a reference voltage and an ADC (Analog-to-Digital Converter) for converting an analog signal to a digital signal on the basis of the reference voltage, and in particular, relates to a reference voltage generation circuit for generating a plurality of reference voltages and a pipe line ADC using the same.
2. Description of the Related Art
A conventional pipe line ADC has a reference voltage generation circuit which generates a plurality of reference voltages to internal circuits. A conventional phase-locked loop circuit (hereinafter “PLL circuit”) also has a reference voltage generation circuit. A reference voltage generation circuit, which generates a plurality of reference voltages to internal circuits having a large circuit dimension, includes an external capacitor with a large capacitance so as to stabilize the reference voltages and decrease electric power consumption. In the reference voltage generation circuit including the external capacitor with a large capacitance, it takes a long time to electrically charge the external capacitor, thus influencing a start-up duration of a pipe line ADC using the reference voltage generation circuit. Various improvements to solve the problem have been proposed. Technologies for overcoming the problem are disclosed in, for example, Japanese Patent Application Laid-Open Publication No. H09-55656 (document D1), Japanese Patent Application Laid-Open Publication No. 2001-168713 (document D2), and Japanese Patent Application Laid-Open Publication No. 2001-285069 (Document D3).
In the document D1, a PLL circuit which decreases a start-up duration at a power down mode is disclosed.
In the document D2, a pipe line ADC is described. In the document D3, an electric potential controlling circuit, which suppresses electric current consumption and decreases a start-up duration, is described.
The conventional pipe line ADC disclosed in the document D2 will now be described with reference to FIGS. 2 to 4 of the accompanying drawings. FIG. 1 is a block diagram showing the conventional pipe line ADC described in the document D2.
As shown in FIG. 1, the conventional pipe line ADC has an analog-to-digital (A/D) conversion part 1, an error correction circuit 16, a timing signal generation circuit 17, and a reference voltage generation circuit 20. The conventional pipe line ADC also has an input terminal VIN, a clock input terminal CLKX, and output terminals D0 to D9. The conventional pipe line ADC inputs continuous analog signals from the input terminal VIN thereof, converts sequentially continuous analog signals to digital signals in response to a clock signal from the clock input terminal CLKX, and then sequentially outputs the digital signals to the output terminals D0 to D9 thereof. The A/D conversion part 1 has pipe line ADC's of nine stages which sequentially convert continuous analog input signals provided from the input terminal VIN to digital signals. The error correction circuit 16, which receives the sequential digital signals generated by the A/D conversion part 1, corrects the digital signals and provides the corrected digital signals (for example, digital signals of ten bits, d0 to d9) to the output terminals D0 to D9, respectively. The timing signal generation circuit 17 generates timing signals trig to the A/D conversion part 1 in response to a clock signal clkx given from the clock input terminal CLKX. The Reference voltage generation circuit 20 outputs reference voltages (refp, vp1, refpq, cm, refnq, vn1, refn) from corresponding reference voltage output terminals (REFP, VP1, REFPQ, CM, REFNQ, REFNQ, VN1, REFN) to the A/D conversion part 1. Internal circuits of the A/D conversion part 1 operate on the basis of the reference voltages (refp, vp1, refpq, cm, refnq, vn1, refn).
The AD conversion part 1 is configured by a sampling and holding circuit 2 and nine pipe line stages (Stg1 to Stg9) 10-1 to 10-9. The nine pipe line stages (Stg1-Stg9) 10-1 to 10-9 are cascade-connected to the sampling and holding circuit 2. The sampling and holding circuit 2 operates on the basis of the reference voltage cm. The sampling and holding circuit 2 samples analog signals given to the input terminal IN in response to the timing signal trig and holds the analog signal for a given duration. The first to eight pipe line stages 10-1 to 10-8, which are cascade-connected to an output terminal of the sampling and holding circuit 2, sequentially convert the output analog signals generated by the sampling and holding circuit 2 into digital signals of 1.5 bits in response to the timing signals trig and the reference voltages refpq, refnq, refp, and refn. The first to eight pipe line stages 10-1 to 10-8 sequentially supply the digital signals of 1.5 bits to the error correction circuit 16. The ninth pipe line stage 10-9 converts an analog signal generated by the eighth pipe line stage 10-8 to a digital signal of 2 bits and supplies the digital signal of 2 bits to the error correction circuit 16 in response to reference voltage vp1, refpq, refnq, vn1, and a timing signal trig.
FIG. 2A is a block diagram showing first to eighth pipe line stages 10-1 to 10-8 (Stg1-Stg8) of FIG. 1, and FIG. 2B is a block diagram showing the ninth pipe line stage 10-9 (Stg9) of FIG. 1.
As shown in FIG. 2A, each of the first to eighth pipe line stages has a sub-ADC 11, a sub-DAC (sub-Digital-to-Analog Converter) 12, and an amplifier 14. Each of the first to eighth pipe line stages also has an input terminal to which an input analog signal vin is supplies and an output terminal from which an output analog signal vout is provided. The sub-ADC 11 compares the input analog signal vin to the reference voltages refpq, refnq, and encodes a resultant comparative signal so as to generate a digital signal of 1.5 bits. The sub-DAC 12 compares the digital signal of 1.5 bits generated by the sub-ADC 11 to the referential voltages refp, refn, and then converts a resultant comparative signal to an analog signal. The subtraction circuit 13 subtracts the analog signal generated by the sub-DAC 12 from the input analog signal vin. The amplifier 14 amplifies the analog signal generated by the subtraction circuit 13 by a factor of two times and then generates the amplified analog signal as an output analog signal vout.
As shown in FIG. 2B, the ninth pipe line stage 10-9 has an sub-ADC 15. The sub-ADC 15 compares an input analog signal vin (the output analog signal vout generated by the eighth pipe line stage 10-8) to the referential voltages vp1, refpq, refnq, and vn1, and encodes a resultant comparative signal so as to generate a digital signal of 2 bits.
FIG. 3 is a block diagram showing the sub-ADC 11 of FIG. 2A. The sub-ADC 11 has comparators 11a, 11b, and an encoder 11c. The comparator 11a and 11b compare an input analog signal vin and the reference voltages refpq, refnq, respectively, and generates resultant comparative signals, respectively. By encoding the respective comparative resultant signals generated by the comparators 11a and 11b, the encoder 11c generates a digital signal.
Operations of the pipe line ADC shown in FIGS. 1 to 3 will now be described. An analog signal given to an input terminal VIN of FIG. 1 is supplied to the sampling and holding circuit 2. The sampling and holding circuit 2 samples and holds the analog signal. And then the analog signal is given to the first pipe line stage 10-1 as a input analog signal vin. In the first pipeline stage 10-1 shown in FIGS. 2A and 3, the comparators 11a and 11b compare the input analog signal vin generated by the sampling and holding circuit 2 to the reference voltages refpq, refnq, respectively. The encoder 11c encodes resultant comparative signals to a digital signal of 1.5 bits. Therefore, the input analog signal vin is converted into the digital signal of 1.5 bits by the first pipe line stage 10-1. The digital signal of 1.5 bits is supplies to the error correcting circuit 16 and the sub-DAC 12.
The sub-DAC 12 converts the digital signal of 1.5 bits from the sub-ADC 11 to an analog signal and supplies the analog signal to the subtraction circuit 13. The subtraction circuit 13 subtracts the analog signal generated by sub-DAC12 from the input analog signal vin and supplied the subtracted analog signal to the amplifier 14. The amplifier 14 amplifies the subtracted analog signal by a factor of two times and supplies the amplified analog signal to the second pipe line stage 10-2.
The second to eighth pipe line stages 10-2 to 10-8 operates in the same way as the first pipe line stage 10-1. An amplified analog signal generated by the eighth pipe line stage is given to the ninth pipe line stage 10-9 as an input analog signal vin. The sub-ADC 15 of the ninth pipe line stage 10-9 shown in FIG. 2B compares an input analog signal vin, which corresponds to the amplified analog signal generated by the eighth pipe line stage, to the reference voltages vp1, refpq, refnq, and vn1 and encodes a resultant comparative signal so as to generate a digital signal of 2 bits to the error correction circuit 16.
The correction circuit 16 sequentially corrects errors in the digital signals respectively generated by the first to ninth pipe line stages 10-1 to 10-9, and supplies the corrected digital signals d0 to d9, each corresponding to the input analog signals from the input terminal VIN, to the output terminals D0 to D9, respectively.
Subsequently, the reference voltage generation circuit 20 shown in FIG. 1 will now be described with reference to FIG. 4. FIG. 4 is a circuit diagram showing the reference voltage generation circuit 20 of FIG. 1. As shown in FIG. 4, the reference voltage generation circuit 20 has an electric current source 21 and nine resistors 22-1 to 22-9, which are arranged in a LSI chip. The electric current source 21 flows a substantially constant electric current. The electric current source 21 has two P channel type MOS transistors (PMOSs) 21a and 21b whose gates are controlled by bias voltages vpbias1 and vpbias2, respectively. The PMOSs 21a and 21b are connected in series across a power terminal VDD and a reference voltage output terminal REFP.
The nine resistors 22-1 to 22-9 are connected in series across the reference voltage output terminal REFP and an earth terminal GND. A reference voltage output terminal VP1 is connected across the resistors 22-1 and 22-2. A reference voltage output terminal REFPQ is connected across the resistors 22-3 and 22-4. A reference voltage output terminal CM is connected across the resistors 22-4 and 22-5. A reference voltage output terminal REFNQ is connected across the resistors 22-5 and 22-6. A reference voltage output terminal VN1 is connected across the resistors 22-7 and 22-8. A reference voltage output terminal REFN is connected across the resistors 22-8 and 22-9.
The reference voltage output terminals REFP and REFN, both of which are provided in the LSI chip, are respectively connected to pads REFP_PAD and REFN_PAD outside the LSI chip. Across the pads REFP_PAD and REFN_PAD, an external capacitor 23 is connected. An input range of the input analog signal of the conventional pipe line ADC is dependent upon a difference between the reference voltage refp on the terminal REFP and the reference voltage refn on the terminal REFN. A reference voltage cm on the terminal CM is utilized as a common mode voltage of the conventional pipe line ADC. Reference voltages vp1, vn1, refpq, and refnq on corresponding reference voltage output terminals VP1, VN1, REFPQ, and REFNQ are utilized as the reference voltages supplied to the comparator 11a and 11b of the conventional ADC.
The reference voltage generation circuit 20 of the conventional pipe line ADC is provided with the external capacitor 23 outside of the LSI chip. The conventional pipe line ADC is turned on at the same time of the generations of the reference voltages and the charging of the external capacitor 23. Thus, it takes much time to increase the difference between the reference voltage refp on the terminal REFP and the reference voltage refn on the terminal REFN to a predetermined level. The difference between the reference voltages is dependent upon the input range of the input analog signal of the ADC. Therefore, there was a difficulty of increasing the time necessary for stabilizing the A/D converting operation after the conventional pipe line ADC is turned on or after the power down mode is released.
To solve the problem, it is considered that technologies disclosed in documents 1 and 3 are applied to the reference voltage generation circuit 20 disclosed in document D2. Since the reference voltage generation circuit 20 is completely different from the circuit structures disclosed in the documents D1 and D3, the technologies disclosed in the documents 1 and 3 can not be simply applied to the conventional reference voltage generation circuit 20, so that the problem has not been easily solved by providing a reference voltage generation circuit having a relatively simple circuit structure.